The present invention relates generally to a non-volatile memory array bias circuit, and more particularly to a bias circuit for virtual ground non-volatile memory array with bank selector.
Non-volatile memory products are very commonly adopted in computer and other electronic products. Non-volatile memory, products include Read Only Memories (ROMs), floating gate-type memories, and Electrically Programmable ROMs (EPROMs). In concert with the development of Very Large Scale Integration (VLSI) processing technology and the development of more and more sophisticated computer and other electronic technologies, the marketplace has placed more and more demands on non-volatile memory products to store more and more data. In order to store more data, smaller cell sizes and higher memory density is certainly the trend demanded by the marketplace. However, some processing factors affect the cell size such as: active pitch, metal line pitch, and contact pitch. Because of these factors, the conventional NOR plan memory cell can not satisfy the above requirements. In order to enhance memory density and to reduce cell size, there is another memory technology called "Flat-Cell Memory" which overcomes the limitations mentioned above, and therefore it has been widely adopted for high density non-volatile memory.
Referring now to FIGS. 1 and 2, FIG. 1 shows an example of a sub-array layout for a conventional flat-cell memory having bank selector; FIG. 2 shows the equivalent circuit schematic for the layout depicted in FIG. 1. For convenience, FIG. 1 only shows one memory bank BK-0; FIG. 2 shows the memory bank BK-0 and partial memory bank BK-1 without details. However, those skilled in the art should know that the structure of BK-1 is the same as BK-0. Also, it should be noted that in these diagrams memory cells are shown in the form of floating gate type Electrically Erasable Programmable ROM (EEPROM) cells; however, the cells could be of the ROM type instead of being of the EEPROM type. The flat-cell memory uses NOR-connected flat-cells to form a virtual ground architecture in order to reduce the size of the memory cell and thus to enhance the memory density. More specifically, the memory bank BK-0 includes a plurality of rows and columns of memory cells (K,0).about.(K,7) . . . , (L,0).about.(L,7) . . . ; word lines WL.sub.-- K.about.WL.sub.-- L; bank select lines SEL.sub.-- OH and SEL.sub.-- OL; and bank select transistors (or bank selectors) 121-0.about.121-8, 122-0.about.122-8. Each memory cell (K,0).about.(K,7), (L,0).about.(L,7) may be programmed to have a low threshold voltage(VT), called "on" cell, or programmed to have a high threshold voltage, called "off" cell. Bank selectors 121-0.about.121-8, 122-0.about.122-8 are all "on" transistors having low threshold voltage. Memory bank BK-1 has the same structure, and for example in a 32.times.32 memory sub-array, also includes a plurality of rows and columns of memory cells (0,0).about.(0,31), . . . ,(31,0).about.(31,31) (these reference numbers are not particularly indicated in the drawings); word lines WL.sub.-- 0.about.WL.sub.-- 31; bank select lines SEL.sub.-- 1H and SEL.sub.-- 1L. This structure uses buried N.sup.+ diffusion regions to form local bit lines 123-0.about.123-8; and metal lines to form data sense bit lines SA-0123, SA-4567, and virtual ground bit lines VG-01, VG-2345, VG-67. Metal lines as shown in FIGS. 1 and 2 are laid out in a zigzag pattern, and the data sense bit lines and the virtual ground bit lines are alternately arranged. Through metal/diffusion contacts, the metal lines are connected to the bank selectors in the form of flat-cell and the buried N.sup.+ local bit lines. At the time of accessing to a cell in flat-cell memory array with bank selectors, the corresponding word lines and bank select lines are activated; and the rest of word lines and bank select lines are deactivated. The signal path is from the corresponding data sense bit line to the buried N.sup.+ local bit line, i.e. the drain of the selected cell, via the "on" bank select transistor. Then, the signal path is from the drain of the selected cell to the source of the selected cell, i.e. the other buried N.sup.+ local bit line at the other side of the selected cell, via the selected cell itself. Finally, the signal path is connected to the virtual ground bit line via the other corresponding bank select transistor.
Reference is now made to FIG. 3 for the details of data access path of memory array. The memory array, similar to the one in FIG. 2, and its column multiplexer are shown here. The column multiplexer includes two stages, and the first stage column multiplexer 201 is used to select a data sense bit line, called the selected data sense bit line, for connecting to current detector. The first stage column multiplexer 201 is also used to select the two virtual ground bit lines adjacent to two sides of the selected data sense bit lines for connecting to the second stage column multiplexer 202. The first stage column multiplexer 201 is composed of transfer gates 111.about.116 which are controlled by the outputs of a column decoder (not shown). Each output line (YSEL) of the column decoder controls three transfer gates of the first stage column multiplexer for connecting the selected data sense bit lines and the two adjacent virtual ground bit lines to the peripheral circuits. The rest of data sense bit lines and virtual ground bit lines are isolated from the peripheral circuits, including the current detector and ground GND, by the turned-off transfer gates in the first stage column multiplexer 201. The second stage column multiplexer 202 is used to select one of the two virtual ground bit lines laterally adjacent to the selected data sense bit line for being grounded, and the other isolated from the ground. The virtual ground bit line which is connected to the ground via the transfer gates 101 and 104 of the second stage column multiplexer, is called the selected virtual ground bit line. The second stage column multiplexer 202 is also composed of transfer gates which are controlled by the outputs of another column decoder (not shown), or an address buffer. The first stage column multiplexer 201 is connected with the current detector via a signal line 250. The second stage column multiplexer 202 is coupled to the first stage column multiplexer 201, and is used to select one of the two virtual ground bit lines output from the first stage column multiplexer 201 for being connected to the ground.
When a cell within the memory array is selected to be accessed, all the corresponding word line, bank select line, and YSEL line are activated, and the rest of them are deactivated. There are four kinds of selected cell conditions which are described in detail hereinafter.
(1) If cell (K,3) is the selected cell, the word-line WL.sub.-- K and bank select line SEL.sub.-- OH are turned to a high logic level; at the same time, the control select lines YSEL-0123 and YA1 of the column multiplexers 201 and 202 are also turned to a high logic level; the rest of word lines, bank select lines, and column multiplexer's control select lines are turned to a low logic level. The signal path, starting from the data line 250, travels via the transfer gate 112 of the column multiplexer 201, to the data sense bit line SA-0123, which is called the selected data sense bit line, and then to the buried N.sup.+ local bit line 123-3 via the bank selector 121-3, and then to the bank selector 121-4 via the selected cell (K,3), and to the virtual ground bit line VG-2345, which is called the selected virtual ground bit line, and finally via the transfer gate 113 in the column multiplexer 201 and the transfer gate 104 in the column multiplexer 202 to ground (GND) 314.
(2) If cell (K,2) is the selected cell, the word-line WL.sub.-- K and bank select line SEL.sub.-- OL are turned to a high logic level; at the same time, the control select lines YSEL-0123 and YA1 of the column multiplexers 201 and 202 are also turned to a high logic level; the rest of word lines, bank select lines, and column multiplexer's control select lines are turned to a low logic level. The signal path, starting from the data line 250, travels via the transfer gate 112 of the column multiplexer 201, to the data sense bit line SA-0123, which is called the selected data sense bit line, and then to the buried N.sup.+ local bit line 123-2 via the bank selector 122-2, and then to the bank selector 122-3 via the selected cell (K,2), and to the virtual ground bit line VG-2345, which is called the selected virtual ground bit line, and finally via the transfer gate 113 in the column multiplexer 201 and the transfer gate 104 in the column multiplexer 202 to ground (GND) 314.
(3) If cell (K,1) is the selected cell, the word-line WL.sub.-- K and bank select line SEL.sub.-- OH are turned to a high logic level; at the same time, the control select lines YSEL-0123 and YA1B of the column multiplexers 201 and 202 are also turned to a high logic level; the rest of word lines, bank select lines, and column multiplexer's control select lines are turned to a low logic level. The signal path, starting from the data line 250, travels via the transfer gate 112 of the column multiplexer 201, to the data sense bit line SA-0123, which is called the selected data sense bit line, and then to the buried N.sup.+ local bit line 123-2 via the bank selector 121-2, and then to the bank selector 121-1 via the selected cell (K,1) and the buried N.sup.+ local bit line 123-1, and to the virtual ground bit line VG-01, which is called the selected virtual ground bit line, and finally via the transfer gate 111 in the column multiplexer 201 and the transfer gate 101 in the column multiplexer 202 to ground (GND) 314.
(4) If cell (K,0) is the selected cell, the word-line WL.sub.-- K and bank select line SEL.sub.-- OL are turned to a high logic level; at the same time, the control select lines YSEL-0123 and YA1B of the column multiplexers 201 and 202 are also turned to a high logic level; the rest of word lines, bank select lines, and column multiplexer's control select lines are turned to a low logic level. The signal path, starting from the data line 250, travels via the transfer gate 112 of the column multiplexer 201, to the data sense bit line SA-0123, which is called the selected data sense bit line, and then to the buried N.sup.+ local bit line 123-1 via the bank selector 122-1, and then to the bank selector 122-0 via the selected cell (K,0) and the buried N.sup.+ local bit line 123-0, and to the virtual ground bit line VG-01, which is called the selected virtual ground bit line, and finally via the transfer gate 111 in the column multiplexer 201 and the transfer gate 101 in the column multiplexer 202 to ground (GND) 314.
From above four exemplary selected cell signal paths, it is to be noted that the word lines are used to activate the memory cells, and the bank select lines are used to select the bank selectors for the signal path. For example, if the selected signal path is through the upper bank selectors of the memory bank BK-0, then bank select line SEL.sub.-- OH is turned to a high logic level. The output control select line, YSEL, of the column decoder is used to determine which line is the selected data sense bit line, and which line is the selected virtual ground bit line, and to connect the selected data sense bit line to the current detector. The control select lines YA1 and YA1B are used to determine which one of the two virtual ground bit lines, laterally adjacent to the selected data sense bit line, is the selected virtual ground bit line, and the other is the deselected virtual ground bit line, and to connect the selected virtual ground bit line to the ground GND. From the foregoing analysis, the bank select line SEL.sub.-- OH is used to select the bank selector for the cells (K,1), (K,3), . . . , and (K,2N+1), where N=0,1,2. . . , and the bank select line SEL.sub.-- 0L is used to select the bank selector for the cells (K,0), (K,2), . . . , and (K,2N). The control select line YSEL-0123 is used to select the selected data sense bit line for the four cells (K,0), (K,1), (K,2), and (K,3); similarly, the control select line YSEL-4567 is used to select the selected data sense bit line for the four cells (K,4), (K,5), (K,6), and (K,7); and the rest of the control select lines of the first stage column multiplexer 201 works in a similar fashion. The control select line YA1 is used to select the selected virtual ground bit line for the selected cells (K,2) and (K,3); or cells (K,6) and (K,7); . . . ; or cells (K,4N+2) and (K,4N+3). The control select line YA1B is used to select the selected virtual ground bit line for the selected cells (K,0) and (K,1); . . . ; or cells (K,4N+0) and (K,4N+1).
As shown in FIGS. 1 and 3, in the fiat-cell memory array structure, when accessing data, all memory cells that are connected to the selected word line are activated. If the cells adjacent to both sides of the selected cell are "ON" cells, the current will flow into the selected cell via these adjacent cells, and vice versa. In this case, the current flowing through the selected cell is not equal to the current through the multiplexer, nor to the current through the current detector. In certain cases, if the difference between the current flowing through the current detector and the current through the selected cell is too large, and the current through the current detector is used to determine the selected storage data, detection errors or delays in detection of the data may be caused. Therefore, a biasing technique has to be utilized to avoid or reduce the current flowing from adjacent "ON" cells into the selected memory cell, or the current flowing from the selected memory cell into adjacent "ON" cells.
The U.S. Pat. No. 4,281,397 discloses a biasing technique, wherein each virtual ground bit line is connected to a diode-type pull-up NMOS transistor. The drains of the transistors are connected to the power source V.sub.dd, and thus to charge the deselected virtual ground bit line to the level of V.sub.dd -V.sub.TH (V.sub.TH is the threshold voltage of the transistors). Besides, the selected virtual ground bit line is pulled down to near the ground by the selected and grounded NMOS transistor, and thus the current leakage of adjacent "ON" cells is reduced. Precisely controlling voltage V.sub.dd can reduce the voltage difference between the deselected virtual ground bit line (V.sub.dd -V.sub.TH) and the selected data sense bit line, and the voltage potential at the drain of the adjacent "ON" cell is very close to the one at the source of the same cell; thus the current leakage of the adjacent "ON" memory cell is so small as to be negligible.
In fact, it is very difficult to obtain a very precise V.sub.dd value because V.sub.dd is generated by a bias circuit and is connected to the static pull-up NMOS transistors of all virtual ground bit lines in the chip. Furthermore, the voltage of the selected data sense bit line is limited by the voltage clamper in each I/O (input/output) current detector. The circuit layouts of these two circuits are far apart, and the circuit connections differ from each other; therefore, it is hard to achieve the process tracking and power noise tracking. If the voltage difference between the selected data sense bit line and the adjacent deselected virtual ground bit line exceeds 0.3 Volt, a noticeable current leakage in the adjacent "ON" cell will occur and this leads to a slow down in accessing data. Another problem is the strength of the static pull-up transistors. The pull-down voltage of the selected virtual ground bit line is influenced by the static pull-up NMOS transistor and the selected and grounded pull-down NMOS transistor. More specifically, if the static pull-up transistor is stronger, the pull-down voltage for the selected virtual ground bit line is higher; thus the current through the selected "ON" cell is smaller, and the access time is longer. On the other hand, if the static pull-up transistor is weaker, and when the selected bit lines are altered to access another cell, the deselected virtual ground bit line which is the previous selected virtual ground bit line and is now adjacent to the new selected cell will be charged from original ground voltage (e.g. about 0.2 V) to the voltage V.sub.dd -V.sub.TH. However, this deselected virtual ground bit line is very hard to be charged to the voltage V.sub.dd -V.sub.TH within one reading cycle due to the weak static pull-up NMOS transistor. Consequently, between the source and the drain of the adjacent "ON" cell there exists a large potential difference which induces a large current leakage through this cell and therefore significantly affects the data access time.
U.S. Pat. No. 5,132,933 discloses another biasing technique which utilizes the sense amplifier bias circuit in the current detector to generate a first predetermined bias voltage for connecting to the selected data sense bit line, and also utilizes another sense amplifier bias circuit to generate a second predetermined bias voltage, which approximately equals the first predetermined bias voltage, for connecting to the deselected virtual ground bit line adjacent to the selected data sense bit line. This makes the drain and the source voltages of the cell adjacent to the selected cell equal, and thus largely reduces current leakage of the adjacent "ON" cell. The rest deselected virtual ground bit lines are connected to a reference potential, i.e. virtual ground potential (normally V.sub.ss), so as to provide the memory array with a discharge path to avoid the charge trapping of virtual ground bit line due to power noise.
However the biasing technique disclosed by the U.S. Pat. No. 5,132,933 is only suitable for a virtual ground memory array without bank selectors. For those memory arrays with bank selectors, this technique will still result in a large current leakage in adjacent "ON" cell. The reason is as follows:
Referring to FIG. 2 or FIG. 3, assume cell (K,1) is the selected cell and is programmed as an "OFF" cell. Also assume that cells (K,2), (K,3), (K,4), (K,5), and (K,6) are programmed as "ON" cells. The selected virtual ground bit line is VG-01; the selected data sense bit line is SA-0123; the deselected virtual ground bit line adjacent to the selected data sense bit line is VG-2345, and the deselected data sense bit line most close to the selected data sense bit line is SA-4567. In this patent, the selected virtual ground bit line VG-01 is pulled down to a virtual ground, the selected data sense bit line SA-0123 is connected to the first predetermined bias voltage, and the deselected virtual ground bit line VG-2345 is connected to the second predetermined bias voltage. Thus the voltage of VG-2345 and the voltage of SA-0123 are very close. However, since the deselected data sense bit line SA-4567 is pulled down to virtual ground (or to a reference voltage), there is a large current (about the same as "ON" cell current) flowing from the deselected virtual ground bit line VG-2345 to the deselected data sense bit line SA-4567. More specifically, this current flows through the network formed by the bank selectors 121-4, 121-5 and cell (K,4), and then through cell (K,5), and finally through the network formed by the bank selectors 121-6, 121-7 and cell (K,6), to the virtual ground of the deselected data sense bit line SA-4567. Since the impedances of the bank selectors and the memory cells approximately equal, this current makes the voltage of the buried N.sup.+ local bit line 123-4 drops to the potential lower than the virtual ground bit line VG-2345, so that a large potential difference exists between the source and the drain of cell (K,3), and this, in turn, induces a current flowing through the cell (K,3). This current flows from the current detector through the data sense bit line SA-0123 and the circuit formed by the bank selectors 121-2, 121-3 and cell (K,2), and then through cell (K,3); consequently, the current detector will detect a large current that causes the error reading on the selected "OFF" cell (K,1). This situation will be improved and the correct data will be detected until the leakage current has charged up the data sense bit line SA-4567 to the potential close to the potential of the data sense bit line SA-0123. Only when this happens, the leakage current decreases to a negligible level, so that the correct data is sensed. However, since the data sense bit lines have large capacitance, about 4.about.8 pf, the charging time of the data sense bit line SA-4567 is very long, and so is the data access time. This degrades the operating speed of the memory device. In conclusion, the biasing technique of this patent pulls down all the deselected data sense bit lines and all the deselected virtual ground bit lines except the one adjacent to the selected cell to virtual ground. Because of the existence of the bank selectors, there is a large induced potential drop between the two buried N.sup.+ local bit lines, all located laterally adjacent to one side of the selected cell which is opposite to the other side of the selected cell to which the selected virtual ground bit line is adjacent. This potential drop induces the current leakage in adjacent "ON" cell, and thus causes the error or delay in data accessing. Therefore, this biasing technique is not suitable for the fiat-cell memory array with bank selector.